aboutsummaryrefslogtreecommitdiffstats
path: root/vendor/golang.org/x/sys/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'vendor/golang.org/x/sys/cpu')
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu.go51
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_arm.go2
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_arm64.go60
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_linux.go61
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_mips64x.go2
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_mipsx.go2
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_ppc64x.go23
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_s390x.go2
-rw-r--r--vendor/golang.org/x/sys/cpu/cpu_x86.go2
9 files changed, 205 insertions, 0 deletions
diff --git a/vendor/golang.org/x/sys/cpu/cpu.go b/vendor/golang.org/x/sys/cpu/cpu.go
index 3d88f8667..6b0034ecd 100644
--- a/vendor/golang.org/x/sys/cpu/cpu.go
+++ b/vendor/golang.org/x/sys/cpu/cpu.go
@@ -29,6 +29,8 @@ var X86 struct {
HasOSXSAVE bool // OS supports XSAVE/XRESTOR for saving/restoring XMM registers.
HasPCLMULQDQ bool // PCLMULQDQ instruction - most often used for AES-GCM
HasPOPCNT bool // Hamming weight instruction POPCNT.
+ HasRDRAND bool // RDRAND instruction (on-chip random number generator)
+ HasRDSEED bool // RDSEED instruction (on-chip random number generator)
HasSSE2 bool // Streaming SIMD extension 2 (always available on amd64)
HasSSE3 bool // Streaming SIMD extension 3
HasSSSE3 bool // Supplemental streaming SIMD extension 3
@@ -36,3 +38,52 @@ var X86 struct {
HasSSE42 bool // Streaming SIMD extension 4 and 4.2
_ CacheLinePad
}
+
+// ARM64 contains the supported CPU features of the
+// current ARMv8(aarch64) platform. If the current platform
+// is not arm64 then all feature flags are false.
+var ARM64 struct {
+ _ CacheLinePad
+ HasFP bool // Floating-point instruction set (always available)
+ HasASIMD bool // Advanced SIMD (always available)
+ HasEVTSTRM bool // Event stream support
+ HasAES bool // AES hardware implementation
+ HasPMULL bool // Polynomial multiplication instruction set
+ HasSHA1 bool // SHA1 hardware implementation
+ HasSHA2 bool // SHA2 hardware implementation
+ HasCRC32 bool // CRC32 hardware implementation
+ HasATOMICS bool // Atomic memory operation instruction set
+ HasFPHP bool // Half precision floating-point instruction set
+ HasASIMDHP bool // Advanced SIMD half precision instruction set
+ HasCPUID bool // CPUID identification scheme registers
+ HasASIMDRDM bool // Rounding double multiply add/subtract instruction set
+ HasJSCVT bool // Javascript conversion from floating-point to integer
+ HasFCMA bool // Floating-point multiplication and addition of complex numbers
+ HasLRCPC bool // Release Consistent processor consistent support
+ HasDCPOP bool // Persistent memory support
+ HasSHA3 bool // SHA3 hardware implementation
+ HasSM3 bool // SM3 hardware implementation
+ HasSM4 bool // SM4 hardware implementation
+ HasASIMDDP bool // Advanced SIMD double precision instruction set
+ HasSHA512 bool // SHA512 hardware implementation
+ HasSVE bool // Scalable Vector Extensions
+ HasASIMDFHM bool // Advanced SIMD multiplication FP16 to FP32
+ _ CacheLinePad
+}
+
+// PPC64 contains the supported CPU features of the current ppc64/ppc64le platforms.
+// If the current platform is not ppc64/ppc64le then all feature flags are false.
+//
+// For ppc64/ppc64le, it is safe to check only for ISA level starting on ISA v3.00,
+// since there are no optional categories. There are some exceptions that also
+// require kernel support to work (DARN, SCV), so there are feature bits for
+// those as well. The minimum processor requirement is POWER8 (ISA 2.07).
+// The struct is padded to avoid false sharing.
+var PPC64 struct {
+ _ CacheLinePad
+ HasDARN bool // Hardware random number generator (requires kernel enablement)
+ HasSCV bool // Syscall vectored (requires kernel enablement)
+ IsPOWER8 bool // ISA v2.07 (POWER8)
+ IsPOWER9 bool // ISA v3.00 (POWER9)
+ _ CacheLinePad
+}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_arm.go b/vendor/golang.org/x/sys/cpu/cpu_arm.go
index d93036f75..7f2348b7d 100644
--- a/vendor/golang.org/x/sys/cpu/cpu_arm.go
+++ b/vendor/golang.org/x/sys/cpu/cpu_arm.go
@@ -5,3 +5,5 @@
package cpu
const cacheLineSize = 32
+
+func doinit() {}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_arm64.go b/vendor/golang.org/x/sys/cpu/cpu_arm64.go
index 1d2ab2902..02ed58b30 100644
--- a/vendor/golang.org/x/sys/cpu/cpu_arm64.go
+++ b/vendor/golang.org/x/sys/cpu/cpu_arm64.go
@@ -5,3 +5,63 @@
package cpu
const cacheLineSize = 64
+
+// HWCAP/HWCAP2 bits. These are exposed by Linux.
+const (
+ hwcap_FP = 1 << 0
+ hwcap_ASIMD = 1 << 1
+ hwcap_EVTSTRM = 1 << 2
+ hwcap_AES = 1 << 3
+ hwcap_PMULL = 1 << 4
+ hwcap_SHA1 = 1 << 5
+ hwcap_SHA2 = 1 << 6
+ hwcap_CRC32 = 1 << 7
+ hwcap_ATOMICS = 1 << 8
+ hwcap_FPHP = 1 << 9
+ hwcap_ASIMDHP = 1 << 10
+ hwcap_CPUID = 1 << 11
+ hwcap_ASIMDRDM = 1 << 12
+ hwcap_JSCVT = 1 << 13
+ hwcap_FCMA = 1 << 14
+ hwcap_LRCPC = 1 << 15
+ hwcap_DCPOP = 1 << 16
+ hwcap_SHA3 = 1 << 17
+ hwcap_SM3 = 1 << 18
+ hwcap_SM4 = 1 << 19
+ hwcap_ASIMDDP = 1 << 20
+ hwcap_SHA512 = 1 << 21
+ hwcap_SVE = 1 << 22
+ hwcap_ASIMDFHM = 1 << 23
+)
+
+func doinit() {
+ // HWCAP feature bits
+ ARM64.HasFP = isSet(HWCap, hwcap_FP)
+ ARM64.HasASIMD = isSet(HWCap, hwcap_ASIMD)
+ ARM64.HasEVTSTRM = isSet(HWCap, hwcap_EVTSTRM)
+ ARM64.HasAES = isSet(HWCap, hwcap_AES)
+ ARM64.HasPMULL = isSet(HWCap, hwcap_PMULL)
+ ARM64.HasSHA1 = isSet(HWCap, hwcap_SHA1)
+ ARM64.HasSHA2 = isSet(HWCap, hwcap_SHA2)
+ ARM64.HasCRC32 = isSet(HWCap, hwcap_CRC32)
+ ARM64.HasATOMICS = isSet(HWCap, hwcap_ATOMICS)
+ ARM64.HasFPHP = isSet(HWCap, hwcap_FPHP)
+ ARM64.HasASIMDHP = isSet(HWCap, hwcap_ASIMDHP)
+ ARM64.HasCPUID = isSet(HWCap, hwcap_CPUID)
+ ARM64.HasASIMDRDM = isSet(HWCap, hwcap_ASIMDRDM)
+ ARM64.HasJSCVT = isSet(HWCap, hwcap_JSCVT)
+ ARM64.HasFCMA = isSet(HWCap, hwcap_FCMA)
+ ARM64.HasLRCPC = isSet(HWCap, hwcap_LRCPC)
+ ARM64.HasDCPOP = isSet(HWCap, hwcap_DCPOP)
+ ARM64.HasSHA3 = isSet(HWCap, hwcap_SHA3)
+ ARM64.HasSM3 = isSet(HWCap, hwcap_SM3)
+ ARM64.HasSM4 = isSet(HWCap, hwcap_SM4)
+ ARM64.HasASIMDDP = isSet(HWCap, hwcap_ASIMDDP)
+ ARM64.HasSHA512 = isSet(HWCap, hwcap_SHA512)
+ ARM64.HasSVE = isSet(HWCap, hwcap_SVE)
+ ARM64.HasASIMDFHM = isSet(HWCap, hwcap_ASIMDFHM)
+}
+
+func isSet(hwc uint, value uint) bool {
+ return hwc&value != 0
+}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_linux.go b/vendor/golang.org/x/sys/cpu/cpu_linux.go
new file mode 100644
index 000000000..a8452e094
--- /dev/null
+++ b/vendor/golang.org/x/sys/cpu/cpu_linux.go
@@ -0,0 +1,61 @@
+// Copyright 2018 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+//+build !amd64,!amd64p32,!386
+
+package cpu
+
+import (
+ "encoding/binary"
+ "io/ioutil"
+ "runtime"
+)
+
+const (
+ _AT_HWCAP = 16
+ _AT_HWCAP2 = 26
+
+ procAuxv = "/proc/self/auxv"
+
+ uintSize uint = 32 << (^uint(0) >> 63)
+)
+
+// For those platforms don't have a 'cpuid' equivalent we use HWCAP/HWCAP2
+// These are initialized in cpu_$GOARCH.go
+// and should not be changed after they are initialized.
+var HWCap uint
+var HWCap2 uint
+
+func init() {
+ buf, err := ioutil.ReadFile(procAuxv)
+ if err != nil {
+ panic("read proc auxv failed: " + err.Error())
+ }
+
+ pb := int(uintSize / 8)
+
+ for i := 0; i < len(buf)-pb*2; i += pb * 2 {
+ var tag, val uint
+ switch uintSize {
+ case 32:
+ tag = uint(binary.LittleEndian.Uint32(buf[i:]))
+ val = uint(binary.LittleEndian.Uint32(buf[i+pb:]))
+ case 64:
+ if runtime.GOARCH == "ppc64" {
+ tag = uint(binary.BigEndian.Uint64(buf[i:]))
+ val = uint(binary.BigEndian.Uint64(buf[i+pb:]))
+ } else {
+ tag = uint(binary.LittleEndian.Uint64(buf[i:]))
+ val = uint(binary.LittleEndian.Uint64(buf[i+pb:]))
+ }
+ }
+ switch tag {
+ case _AT_HWCAP:
+ HWCap = val
+ case _AT_HWCAP2:
+ HWCap2 = val
+ }
+ }
+ doinit()
+}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_mips64x.go b/vendor/golang.org/x/sys/cpu/cpu_mips64x.go
index 6165f1212..f55e0c82c 100644
--- a/vendor/golang.org/x/sys/cpu/cpu_mips64x.go
+++ b/vendor/golang.org/x/sys/cpu/cpu_mips64x.go
@@ -7,3 +7,5 @@
package cpu
const cacheLineSize = 32
+
+func doinit() {}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_mipsx.go b/vendor/golang.org/x/sys/cpu/cpu_mipsx.go
index 1269eee88..cda87b1a1 100644
--- a/vendor/golang.org/x/sys/cpu/cpu_mipsx.go
+++ b/vendor/golang.org/x/sys/cpu/cpu_mipsx.go
@@ -7,3 +7,5 @@
package cpu
const cacheLineSize = 32
+
+func doinit() {}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_ppc64x.go b/vendor/golang.org/x/sys/cpu/cpu_ppc64x.go
index d10759a52..ed975de62 100644
--- a/vendor/golang.org/x/sys/cpu/cpu_ppc64x.go
+++ b/vendor/golang.org/x/sys/cpu/cpu_ppc64x.go
@@ -7,3 +7,26 @@
package cpu
const cacheLineSize = 128
+
+// HWCAP/HWCAP2 bits. These are exposed by the kernel.
+const (
+ // ISA Level
+ _PPC_FEATURE2_ARCH_2_07 = 0x80000000
+ _PPC_FEATURE2_ARCH_3_00 = 0x00800000
+
+ // CPU features
+ _PPC_FEATURE2_DARN = 0x00200000
+ _PPC_FEATURE2_SCV = 0x00100000
+)
+
+func doinit() {
+ // HWCAP2 feature bits
+ PPC64.IsPOWER8 = isSet(HWCap2, _PPC_FEATURE2_ARCH_2_07)
+ PPC64.IsPOWER9 = isSet(HWCap2, _PPC_FEATURE2_ARCH_3_00)
+ PPC64.HasDARN = isSet(HWCap2, _PPC_FEATURE2_DARN)
+ PPC64.HasSCV = isSet(HWCap2, _PPC_FEATURE2_SCV)
+}
+
+func isSet(hwc uint, value uint) bool {
+ return hwc&value != 0
+}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_s390x.go b/vendor/golang.org/x/sys/cpu/cpu_s390x.go
index 684c4f005..ce8a2289e 100644
--- a/vendor/golang.org/x/sys/cpu/cpu_s390x.go
+++ b/vendor/golang.org/x/sys/cpu/cpu_s390x.go
@@ -5,3 +5,5 @@
package cpu
const cacheLineSize = 256
+
+func doinit() {}
diff --git a/vendor/golang.org/x/sys/cpu/cpu_x86.go b/vendor/golang.org/x/sys/cpu/cpu_x86.go
index 71e288b06..2b3ca2e11 100644
--- a/vendor/golang.org/x/sys/cpu/cpu_x86.go
+++ b/vendor/golang.org/x/sys/cpu/cpu_x86.go
@@ -27,6 +27,7 @@ func init() {
X86.HasPOPCNT = isSet(23, ecx1)
X86.HasAES = isSet(25, ecx1)
X86.HasOSXSAVE = isSet(27, ecx1)
+ X86.HasRDRAND = isSet(30, ecx1)
osSupportsAVX := false
// For XGETBV, OSXSAVE bit is required and sufficient.
@@ -47,6 +48,7 @@ func init() {
X86.HasAVX2 = isSet(5, ebx7) && osSupportsAVX
X86.HasBMI2 = isSet(8, ebx7)
X86.HasERMS = isSet(9, ebx7)
+ X86.HasRDSEED = isSet(18, ebx7)
X86.HasADX = isSet(19, ebx7)
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 12:12:54 +0800