aboutsummaryrefslogtreecommitdiffstats
path: root/core
diff options
context:
space:
mode:
authorJhih-Ming Huang <jm.huang@cobinhood.com>2019-03-15 17:36:14 +0800
committerJhih-Ming Huang <jm.huang@cobinhood.com>2019-05-06 10:44:04 +0800
commit6d6da8295a287039805e8ed070c8b57ec3e70caa (patch)
treea793c993fc3b470295ac50c640f6257e7797b883 /core
parent9e8e6408e3c1aafab1b09e5eaed6bf3e7d02e6a7 (diff)
downloaddexon-6d6da8295a287039805e8ed070c8b57ec3e70caa.tar
dexon-6d6da8295a287039805e8ed070c8b57ec3e70caa.tar.gz
dexon-6d6da8295a287039805e8ed070c8b57ec3e70caa.tar.bz2
dexon-6d6da8295a287039805e8ed070c8b57ec3e70caa.tar.lz
dexon-6d6da8295a287039805e8ed070c8b57ec3e70caa.tar.xz
dexon-6d6da8295a287039805e8ed070c8b57ec3e70caa.tar.zst
dexon-6d6da8295a287039805e8ed070c8b57ec3e70caa.zip
core: vm: sqlvm: runtime: add loadRegister func
Implement load register to input operands, before each op.
Diffstat (limited to 'core')
-rw-r--r--core/vm/sqlvm/runtime/instructions.go2
-rw-r--r--core/vm/sqlvm/runtime/runtime.go9
2 files changed, 10 insertions, 1 deletions
diff --git a/core/vm/sqlvm/runtime/instructions.go b/core/vm/sqlvm/runtime/instructions.go
index 9ecc41231..668da692c 100644
--- a/core/vm/sqlvm/runtime/instructions.go
+++ b/core/vm/sqlvm/runtime/instructions.go
@@ -57,5 +57,5 @@ type Operand struct {
IsImmediate bool
Meta []ast.DataType
Data []Tuple
- RegisterIndex *int
+ RegisterIndex uint
}
diff --git a/core/vm/sqlvm/runtime/runtime.go b/core/vm/sqlvm/runtime/runtime.go
index a8f8db7ee..8c3a105ac 100644
--- a/core/vm/sqlvm/runtime/runtime.go
+++ b/core/vm/sqlvm/runtime/runtime.go
@@ -10,6 +10,7 @@ import (
func Run(stateDB vm.StateDB, ins []Instruction, registers []*Operand) (ret []byte, err error) {
for _, in := range ins {
opFunc := jumpTable[in.Op]
+ loadRegister(in.Input, registers)
errCode := opFunc(&common.Context{}, in.Input, registers, in.Output)
if errCode != nil {
err = errors.Error{
@@ -23,3 +24,11 @@ func Run(stateDB vm.StateDB, ins []Instruction, registers []*Operand) (ret []byt
// TODO: ret = ABIEncode(ins[len(ins)-1].Output)
return
}
+
+func loadRegister(input, registers []*Operand) {
+ for i, operand := range input {
+ if operand != nil && !operand.IsImmediate {
+ input[i] = registers[operand.RegisterIndex]
+ }
+ }
+}